1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly to a semiconductor device having silicon on insulator (SOI) and a fabricating method therefor, by which a distance between a diode and a well resistor of the SOI semiconductor device is shortened to achieve high integration without degradation in insulating characteristics in the device.
2. Description of the Prior Art
Recently, great attention has been drawn to the SOI technique, in which a monocrystalline silicon layer is formed on an insulating layer to integrate semiconductor unit elements. If the SOI technique is applied to fabricating a semiconductor device, it can reduce junction capacitance in driving the semiconductor device, so as to improve its operational speed compared with a general bulk semiconductor device.
However, due to a structural characteristic of the SOI semiconductor device, a silicon substrate and a unit device formed thereon are completely separated by an insulating layer, commonly referred to as a buried oxide (BOX) layer. As a result, a unit element like a diode is typically formed as a lateral element for integrating electronic circuits on the SOI substrate, causing a limitation in use of a well structured element such as a resistor for integrated circuits. As a result, the diode has not been made in the vertical NPN (or PNP) structure commonly used for an electro static discharge (ESD) circuit or the like, causing difficulty in fabricating an integrated circuit.
If a vertical NPN (or PNP) diode is replaced by lateral NPN (or PNP) diode, the driving capacity is reduced to approximately half. Therefore, it is necessary to fabricate the unit element (diode) of the vertical NPN structure twice as large as that of the horizontal NPN structure to compensate for this disadvantage. Accordingly, the area is also proportionally required for fabricating a larger unit element, resulting in a negative effect on the integration level of the highly integrated circuit.
Therefore, in order to allow such a unit element to be fabricated in the same structure within the same area as used for a conventional semiconductor device, the SOI semiconductor device is fabricated by selectively etching a predetermined portion of the upper silicon layer and BOX layer, and forming the unit elements inside a lower silicon layer.
FIG. 1 is a cross-sectional view illustrating a conventional structure of a SOI semiconductor device fabricated according to the aforementioned method. The conventional structure of FIG. 1 includes a semiconductor device having a diode.
According to the cross-sectional view in FIG. 1, the conventional SOI device includes a SOI substrate having a surface silicon layer 10c formed by inserting an insulating layer 10b on a P type semiconductor substrate 10a. An element separating layer 12 is formed at a predetermined portion (an element separating region) of the surface silicon layer 10c for enabling its bottom surface to contact the insulating layer 10b. A gate electrode 16 is formed by inserting a gate insulating layer 14 at a predetermined portion of the surface silicon layer 10c. An insulating spacer 20 is formed at both side walls of the gate electrode. A source/drain region 22 is formed in the surface silicon layer 10c at both edges of the gate electrode 16 for enabling its bottom part to contact the insulating layer 10b. A first groove (g1) formed at one side of the gate electrode 16 for penetrating the surface silicon layer 10c and insulating layer 10b to expose a predetermined portion of an active region of a N well 24 formed inside the semiconductor substrate 10a. A P type first diffusion region 26 is formed inside the N well 24 at the bottom of the first groove (g1). A second groove (g2) is formed at one side of the first diffusion region 26 by penetrating the surface silicon layer 10c and insulating layer 10b to expose a predetermined portion of the active region of the silicon substrate 10. A N+ type second diffusion region 28 is formed in the silicon substrate 10a under the second groove (g2). An interlevel insulating layer 30 having a plurality of contact holes (h) is formed on the resultant structure to expose a predetermined portion of the surface of the first and second diffusion regions 26, 28. Metal wires 32 are formed for separately connecting the first and second diffusion regions 26, 28. Item 18 is a silicide layer formed for reducing voltage levels of the gate electrode and contact wires.
Accordingly, in case of the SOI device thus constructed, a surface silicon layer 10c surrounded by insulating layer 10b and device separating layer 12 is used for a transistor channel region, the first diffusion region 26 and N well 24 for P+/N diode, and the second diffusion region 28 and P type silicon substrate 10a for N+/P diode.
However, there are several drawbacks to the SOI device thus constructed. The distance I between the N well 24 formed for the P+/N diode and the second diffusion region 28 formed for the N+/P diode is reduced enough to allow the N well 24 and the second diffusion region 28 to meet each other in the silicon substrate 10a. At this time, the silicon substrate 10a does not have a function for separation to thereby reduce the operational property of the semiconductor device. Therefore, it is very important to secure a sufficient distance between those diodes of the SOI semiconductor device constructed in the structure shown in FIG. 1. Therefore, there are problems in the conventional method for fabricating the SOI semiconductor device in that there is given a limitation in shortening the distance between diodes for fabricating a highly integrated semiconductor device according to designing rules.